Memory controllers communicate signals containing data, addresses or commands to one or more memory integrated circuits (ICs) through signal lines (which are also referred to as ‘links’). In many memory systems, one or more links constitute a shared resource. For example, a memory IC (such as dynamic random-access memory or DRAM) may retrieve read data from an address in its memory core and may provide the read data to a memory controller via a bidirectional link between the memory controller and the memory IC. If the bidirectional link uses half-duplex communication, the memory controller may subsequently provide write data to the memory IC also via the bidirectional link.
However, a turnaround delay typically occurs when the memory controller transitions from receiving the read data to providing the write data via a link. This delay is associated with the round-trip time from the bidirectional link to the memory core and back again, as well as from delays through an interface in the memory IC. Hence, if alternating bursts of read and write data are communicated on the bidirectional link, gaps need to be included in the data stream to account for the turnaround delay, which reduces the effective data rate and the efficiency of communication between the memory controller and the memory IC.
Table 1 provides communication directions on bidirectional links during four operating modes in the memory system of FIG. 1A.